BaBar Level-1 Drift Chamber Trigger Upgrade

submitted to the Xth VCI 2004 30 November 2003 This BaBar L1 DCT upgrade is essential for improving L1 trigger background rejection in preparation for the expected increase in PEP-II luminosity. A large fraction of the current L1 trigger background come from interactions of beam particles with beam line components at ∼ ±20 cm from the interaction point (IP), along the beam direction (z axis). The upgrade DCT has a novel design which uses the drift time information and stereo wires in the drift chamber to perform fast 3D track reconstruction, to effectively reject background originating away from IP in z. The L1 trigger operates in a continuous sampling mode, generating trigger information at regular, fixed time intervals. The DCT consists of 33 9U Eurocards forming the bulk of the BaBar L1 hardware trigger. The upgrade modules all used XILINX Virtex-II FPGAs, with their large logic capacity and internal RAMs matching well to our design needs. The DCT upgrade system consists of 24 replacement Track Segment Finder (TSF) modules, 8 new Z-Pt-Discriminator (ZPD) modules, 1 Binary Link Tracker (BLT) module from the existing system and various interface connection modules. The segment finding in TSF and track reconstruction in ZPD each takes ∼ 2μs. The input data to the DCT consist of one bit for each of the 7104 drift chamber cells, updated every 269 ns. These bits convey time information derived from the sense wire signal for that cell. The 40 wire layers of the drift chamber are radially grouped into 10 superlayers, with 4 axial and 6 stereo superlayers. The TSFs search for track segments in each superlayer, based on the wire hit pattern and time development information. The useful track segment patterns are calibrated using data and stored in a look-up table. The segment spatial resolution achieved is ∼ 800μm. The fine resolution TSF data transferred to the ZPD via LVDS channel link now allow more elaborate 3D track reconstruction. Each ZPD board processes up to 12 track candidates from a 45◦ wedge in azimuth. The large amount of input TSF data are distributed to the 6 algorithm XILINX XC2V4000 FPGAs via a bus of 75 LVDS pairs at 120MHz. The track reconstruction uses Hough transform for pattern recognition followed by a linear fit in the rz view. Trigger requirement can use a combination of cuts on the reconstructed track z0, Pt and tanλ. The track reconstruction is efficient down to Pt of 250MeV/c and the z0 resolution is ∼ 4 cm. Following the successful prototype tests, the ZPD and most of the interface boards have already completed production and the TSF production has started in Oct/03. A partial new system of 1/8 of the detector has been installed and taking data in BaBar regularly since Sep/03 in parallel with the existing system. A complete new DCT system will be commissioned in Jan/04. We will present in the paper the initial performance of the new DCT system from the full system commissioning.